The present invention is directed, in general, to a semiconductor device and a method of manufacturing that device and, more specifically, to a flash memory device having a bipolar transistor associated therewith and a method of manufacture therefore.
Memory devices, such as flash memory devices, have been employed in numerous electronic technologies, and thus, have accounted for a large number of the integrated circuits (IC""s) produced. Simplicity in design and relative ease in taking advantage of new technological advances have made these memory devices a natural vehicle for technology development. Over the last decade, the operating speeds and packing densities of IC""s have increased substantially while the device size has been dramatically reduced. With the dramatic decrease in device size, it is highly desirable to lower the input voltage of those IC""s. This was a result of reduced breakdown voltage and increased power dissipation problems associated with the increased packing density and decreased device size. The combination of increased packing density, device size reduction, and more specifically, reduced operating voltage, have affected the speed at which the memory devices function, which has been particularly acute in flash memory device technologies.
As various technologies have advanced, the need for memory devices that function at faster speeds has grown. Thus, a highly desirable requirement of a flash memory device is that it can read quickly (i.e., have a fast read time). Fast reading speeds require that the flash memory devices have a high charging current that can easily and quickly charge the load capacitance. However, decreasing the device voltage, as described above, makes the available charging current decrease (assuming the current depends on a fixed value of resistance), thus, increasing the read time. The charging current may be maintained, or even increased, even though the device voltage is decreased, but this requires decreasing the resistance within the flash memory device. This situation results in increased power to the chip, which in turn brings about undesirable power dissipation.
In an attempt to provide a faster flash memory device, the IC industry has developed various types of flash memory devices of varying structure and design. Often, these flash memory devices require additional fabrication steps that add to the overall cost of the semiconductor device into which the flash memory is incorporated. Moreover, the resulting flash memory may still lack the desired reading speed. While these attempts may have somewhat increased the reading speeds of flash memory devices, there remains a gap in the reading speed memory devices and the amount of data that needs to be downloaded, and the expectations of the end user. One technology where this problem often arises is digital cameras, where a graphical image may often consist of several megabytes of data. Slower read times result in a slower download of the transmitted data. Given the overall general increase in the speed of today""s ICs, the end user expects faster download times as well. Furthermore, the sheer amount of data that often needs to be downloaded is also constantly increasing.
Accordingly, what is needed in the art is a flash memory device capable of operating at substantially lower read times and that may be manufactured inexpensively with as few a number of fabrication steps as possible. The present invention addresses these needs.
To address the above-discussed deficiencies of the prior art, the present invention provides a bipolar transistor for use in increasing a speed of a flash memory cell having a source region, a drain region, and first and second complementary tubs. In a preferred embodiment, a base for the bipolar transistor is located in the first complementary tub of the flash memory cell, the first complementary tub also functioning as a collector for the bipolar transistor. The bipolar transistor base also uniquely functions as the source region of the flash memory cell. The bipolar transistor""s emitter is also located in the first complementary tub, and proximate the base. For example, the emitter may be located adjacent the base or be actually located in the base region itself. In an additional embodiment, opposing bases and emitters are located on opposing sides of and proximate to the flash memory cell.
Thus, in a broad sense, the present invention provides a flash memory device having both high reading speeds and low power dissipation. The flash memory device includes a bipolar transistor that allows for a smaller resistance to be placed in the flash memory device, which increases the reading speed. When the transistor is located in a closed position, it allows the charging current to charge the capacitance at a fast rate. However, when the transistor is located in the open position, no charging current is present, thus no power dissipation occurs except for a small amount of leakage.